VLSI VHDL Labs

 Lab 7 - Labs using VHDL - VGA Timing Control Laboratory Objectives The objectives of this laboratory are: ·         Create a VGA interface interfacing the FPGA with a monitor ·         Prototype the design on the Terasic DE1-SoC FPGA board ·         Understand the timing reports before and after place and route FPGA Design The following   is to   draw a blue square over a yellow background on the monitor as shown in the picture below The VGA controller should generate the entire control signal to drive the VGA output of the development board. The  controller should have the following architecture: Figure 1 Typical Block Diagram of VGA Controller (Click to enlarge) Reference: http://eewiki.net/pages/viewpage.action?pageId=15925278 Background VGA is a standard interface for controlling the ana...